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Title: | Breaking the Memory Wall in MonetDB |
Authors: | Gopika S |
Keywords: | MonetDB database |
Issue Date: | 10-Jun-2011 |
Abstract: | The rate of improvement in microprocessor speed exceeds the rate of
improvement in DRAM memory speed — each is improving exponentially,
but the exponent for microprocessors is substantially larger than that for
DRAMs. The difference between diverging exponentials also grows
exponentially. Main-memory access has therefore become a performance
bottleneck for many computer applications; a phenomenon that is widely
known as the “memory wall.” This report focuses on how research around the
MonetDB database system has led to a redesign of database architecture in
order to take advantage of modern hardware, and in particular to avoid hitting
the memory wall. This encompasses (i) a redesign of the query execution
model to better exploit pipelined CPU architectures and CPU instruction
caches; (ii) the use of columnar rather than row-wise data storage to better
exploit CPU data caches; (iii) the design of new cache-conscious query
processing algorithms; and (iv) the design and automatic calibration of
memory cost models to choose and tune these cache-conscious algorithms in
the query optimizer. |
URI: | http://hdl.handle.net/123456789/3501 |
Appears in Collections: | MTech 2009-2011 Batch
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