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Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/2014

Authors: Akshita K.A
Keywords: Accelerator based HPC
Issue Date: 6-Jan-2011
Abstract: High-performance computing (HPC) uses supercomputers and computer clusters to solve advanced computation problems. HPC has come to be applied to business uses of cluster-based supercomputers, such as data warehouses, line-of-business (LOB) applications, and transaction processing. In the past few years, a new class of HPC systems has emerged. These systems employ unconventional processor architectures—such as IBM's Cell processor and graphics processing units (GPUs)—for heavy computations and use conventional central processing units (CPUs) mostly for non-compute-intensive tasks, such as I/O and communication. Prominent examples of such systems include the Los Alamos National Laboratory's Cell-based Roadrunner) and the Chinese National University of Defence Technology's ATI GPU-based Tianhe-1 cluster. The main reason computational scientists consider using accelerators is because of the need to increase application performance to either decrease the compute time, increase the size of the science problem that they can compute, or both. The HPC space is challenging since its dominated by applications that use 64 bit floating point calculations and have frequent data reuse. As the size of conventional HPC systems increase, their space and power requirements and operational cost quickly outgrow the available resources and budgets. Thus, metrics such as flops per machine footprint, flops per watt of power, or flops per dollar spent on the hardware and its operation are becoming increasingly important. Accelerator-based HPC systems look particularly attractive considering these metrics. Types of accelerators in use 1. General purpose Graphical Processing units( GPGPUs) - a specialized microprocessor that offloads and accelerates 3D or 2D graphics rendering from the microprocessor. 2. Field Programmable Gate arrays( FPGAs)- an array of logic gates that can be hardware-programmed to fulfil user-specified tasks. 3 .Clear Speed Floating point accelerators 4. IBM Cell processors.
Description: Seminar report submitted in Sept 2010 in partial fulfillment of the requirements for the Degree of Bachelor of Technology (B.Tech ) in Computer Science and Engineering under the Guideship of Sheena S.
URI: http://hdl.handle.net/123456789/2014
Appears in Collections:Seminar Reports

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